Verilog RTL I
Combinational/sequential/ALU/timer
Assessment timing: End of Week 2, after Day 10.
Workbook requirement
Primary deliverable
RTL + TB + waveform
Workbook expectation
Pass expectation
Compiles, simulates, handles corner cases
01Complete Week 2 learning
→02Finish guided & independent labs
→03Debug and verify
→04Prepare deliverable
→05Assessment / review
This page currently defines the workbook assessment requirement. Detailed question-level assessment content has not yet been authored for this week.