Instructor-led programme roadmap

VLSI Front-End Design & Verification — 8-Week Training Plan

Lab-intensive; specification → code → simulate → debug → verify. The roadmap shows the complete planned programme; unpublished SystemVerilog, SVA/Coverage and UVM learning remains marked Coming Soon.

View 8-week plan ↓Assignments & evaluation
8Weeks
40Working days
280Total hours
7hPer day
Daily learning model

Every day is built around doing, not only reading.

2hTheory
→
2hGuided Lab
→
2hIndependent Lab
→
1hDebug / Assignment
Programme schedule

8 weeks · 40 training days

Weeks 1–4 align to the currently published foundation/Verilog learning. Weeks 5–8 are shown for programme transparency and remain Coming Soon on the public platform.

WEEK 1

Foundation

Current learning scope

Focus: Linux, GVim, Shell, Digital Design, Basic C++

Lab emphasis: Tool fluency + design fundamentals

Day 1Foundation – Linux7h
Theory · 2h

Linux role in VLSI
Filesystem hierarchy; absolute/relative paths
Files/directories; permissions
stdin/stdout; pipes and redirection

Guided Lab · 2h

1. Navigation: pwd/cd/ls
2. Create project_workspace project tree
3. File create/copy/move/delete
4. cat/less/head/tail
5. chmod and permission practice

Independent Lab · 2h

6. Build project_workspace for VLSI work
7. Batch-create files/directories
8. Search and organize files by extension
9. Reproduce project_workspace without notes

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Fix 10 incorrect Linux commands
Prepare 30-command Linux reference sheet

Complete this work before closing Day 1.
WHAT YOU MUST COMPLETEExpected deliverable

Working project_workspace + command reference

DAY 1 EXPERIMENT SHEET

Build a reproducible Linux workspace and demonstrate safe filesystem and permission handling for VLSI work.

Setup
  1. Open a terminal in your home directory.
  2. Use project_workspace as the root directory for all Week 1 work.
  3. Keep a terminal transcript or screenshots as evidence.
Execution steps
  1. Run pwd, ls and cd to confirm your starting location.
  2. Create project_workspace with rtl, tb, scripts, logs and docs subdirectories.
  3. Create sample files, then practise cp, mv and rm without leaving the workspace.
  4. Inspect files with cat, less, head and tail.
  5. Apply and verify file permissions with chmod and ls -l.
  6. Search and organize sample .v, .sv and .log files by extension.
Debug challenge

Correct the 10 incorrect Linux commands listed by the instructor and explain what was wrong with each command.

Evidence to keep
  • project_workspace directory tree
  • terminal output showing navigation and permissions
  • 30-command Linux reference sheet
Completion criteria
  • Workspace can be recreated without notes
  • Commands run without path errors
  • Permissions are demonstrated and explained
Continue in Learn: Linux Fundamentals

The corresponding public course is not published yet.

Day 2Foundation – Linux/GVim7h
Theory · 2h

grep/find/sort/uniq/diff/cut/tee
Processes: ps/top/jobs/bg/fg/kill/nohup
Environment variables and PATH
GVim modes, search/replace, tabs, splits, visual block

Guided Lab · 2h

1. Extract ERROR/WARNING/PASS/FAIL from logs
2. Find .v/.sv/.log files
3. Compare RTL revisions with diff
4. Edit Verilog in GVim
5. Search/replace signal names

Independent Lab · 2h

6. GVim split RTL/TB view
7. Multi-tab editing
8. Visual block column edits
9. Verilog indentation/syntax highlighting
10. Regression log filtering

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Create .vimrc for RTL/DV work
Find and correct formatting errors in a sample RTL file

Complete this work before closing Day 2.
WHAT YOU MUST COMPLETEExpected deliverable

.vimrc + GVim-edited RTL/TB files in project_workspace

DAY 2 EXPERIMENT SHEET

Use Linux text/process tools and GVim efficiently for RTL/DV editing and regression-log inspection.

Setup
  1. Reuse project_workspace from Day 1.
  2. Place sample RTL, TB and log files inside the workspace.
  3. Open files using GVim.
Execution steps
  1. Extract ERROR, WARNING, PASS and FAIL lines with grep.
  2. Locate .v, .sv and .log files with find.
  3. Compare two RTL revisions with diff.
  4. Open RTL/TB in GVim splits and multiple tabs.
  5. Search and replace a signal name safely.
  6. Use visual block editing for a column change.
  7. Create a minimal .vimrc suitable for RTL/DV editing.
Debug challenge

Find and correct formatting problems in the instructor-provided sample RTL file, then show the before/after difference.

Evidence to keep
  • .vimrc
  • edited RTL/TB files
  • filtered regression-log output
  • diff output
Completion criteria
  • GVim split/tab workflow demonstrated
  • Search/replace completed without unintended edits
  • Log filtering produces the requested categories
Continue in Learn: Linux + GVim

The corresponding public course is not published yet.

Day 3Foundation – Shell Automation7h
Theory · 2h

Bash variables/arguments
if/case/for/while
Functions and exit status
Environment setup; simulation scripts
Basic Makefile concept

Guided Lab · 2h

1. hello.sh
2. Command-line argument handling
3. File existence check
4. Loop through .v files
5. PASS/FAIL log counter

Independent Lab · 2h

6. run_sim.sh: compile/run/log
7. clean.sh
8. setup_env.sh
9. Timestamp regression outputs
10. Simple Makefile target flow

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug a broken shell script
Create one-command simulation flow

Complete this work before closing Day 3.
WHAT YOU MUST COMPLETEExpected deliverable

Reusable simulation automation scripts

DAY 3 EXPERIMENT SHEET

Automate a repeatable command-line simulation workflow using Bash and a simple Makefile flow.

Setup
  1. Work under project_workspace/scripts and project_workspace/logs.
  2. Use executable shell scripts with a valid shebang.
  3. Do not hard-code machine-specific absolute paths.
Execution steps
  1. Create hello.sh and verify execution permissions.
  2. Read command-line arguments and validate missing input.
  3. Check whether an input file exists and return a meaningful exit status.
  4. Loop through .v files and print the discovered list.
  5. Count PASS and FAIL entries in a sample log.
  6. Create run_sim.sh with compile, run and log stages.
  7. Create clean.sh and setup_env.sh.
  8. Add timestamps to regression output directories.
  9. Create a simple Makefile target that invokes the workflow.
Debug challenge

Repair the broken shell script supplied by the instructor and demonstrate one-command execution of the corrected flow.

Evidence to keep
  • hello.sh
  • run_sim.sh
  • clean.sh
  • setup_env.sh
  • Makefile
  • sample log and PASS/FAIL summary
Completion criteria
  • Scripts return sensible exit status
  • One command runs the intended flow
  • Generated output is stored under project_workspace
Continue in Learn: Shell Automation

The corresponding public course is not published yet.

Day 4Foundation – Digital Design7h
Theory · 2h

Number systems and signed arithmetic
Boolean algebra and gates
Combinational logic
MUX/decoder/encoder/comparator
Adder/subtractor/parity

Guided Lab · 2h

1. Number conversions
2. Two's complement
3. Boolean simplification
4. Half/full adder truth tables
5. 2:1/4:1 MUX

Independent Lab · 2h

6. Decoder
7. Priority encoder
8. Comparator
9. Parity generator/checker
10. Paper-design 4-function ALU

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Solve 10 logic design problems
Prepare equations and block diagram for 4-bit ALU

Complete this work before closing Day 4.
WHAT YOU MUST COMPLETEExpected deliverable

Digital design worksheet + ALU architecture

DAY 4 EXPERIMENT SHEET

Apply combinational digital-design fundamentals and produce a clear 4-bit ALU paper architecture.

Setup
  1. Use the Digital Design course as the reference learning material.
  2. Show intermediate steps for conversions and Boolean simplification.
  3. Keep the worksheet in project_workspace/docs.
Execution steps
  1. Complete binary/decimal/hexadecimal conversions.
  2. Solve signed two's-complement examples.
  3. Simplify the assigned Boolean expressions.
  4. Create half-adder and full-adder truth tables and equations.
  5. Derive 2:1 and 4:1 MUX behaviour.
  6. Design decoder, priority encoder, comparator and parity functions.
  7. Paper-design a 4-function, 4-bit ALU with operation select, block diagram and equations.
Debug challenge

Solve the 10 logic-design problems supplied by the instructor and identify any incorrect truth-table/equation assumptions.

Evidence to keep
  • completed digital-design worksheet
  • truth tables/equations
  • 4-bit ALU block diagram and operation table
Completion criteria
  • Conversions and signed arithmetic are correct
  • Combinational equations match truth tables
  • ALU architecture clearly identifies inputs, outputs and select behaviour
Continue in Learn: Digital Design

The corresponding public course is not published yet.

Day 5Foundation – Sequential + Basic C++7h
Theory · 2h

Latch/flip-flop/register/counter
Clock/reset; Moore/Mealy FSM
C++ variables, loops, functions, arrays, strings
References, pointers, classes, constructors, inheritance

Guided Lab · 2h

1. DFF timing
2. Register/shift register
3. Counter
4. Moore vs Mealy sequence detector
5. C++ calculator
6. Array min/max

Independent Lab · 2h

7. String handling
8. Function/reference/pointer exercises
9. Transaction class
10. Constructor
11. Base/derived transaction classes

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-1 practical: Linux + GVim + C++
20-minute digital design quiz

Complete this work before closing Day 5.
WHAT YOU MUST COMPLETEExpected deliverable

Foundation assessment + C++ transaction model

DAY 5 EXPERIMENT SHEET

Connect sequential-logic reasoning with Basic C++ programming and build the Week 1 transaction model.

Setup
  1. Use the Digital Design course for sequential-logic reference material.
  2. Create C++ work under project_workspace/cpp.
  3. Compile and run the transaction example from the command line.
Execution steps
  1. Analyse DFF timing and reset behaviour.
  2. Work through register, shift-register and counter behaviour.
  3. Compare Moore and Mealy sequence-detector structure.
  4. Write a small C++ calculator and array min/max exercise.
  5. Practise strings, functions, references and pointers.
  6. Implement a transaction class with fields, constructor and print/display behaviour.
  7. Create a base/derived transaction example to demonstrate inheritance.
Debug challenge

Complete the Week 1 Linux + GVim + C++ practical and the 20-minute digital-design quiz before starting the Foundation Assessment.

Evidence to keep
  • sequential-logic notes/quiz
  • C++ source
  • transaction class output
  • base/derived class example
Completion criteria
  • C++ code compiles and runs
  • Transaction object output is understandable
  • Learner can explain basic sequential behaviour and the C++ class structure
Continue in Learn: Sequential Logic; C++ is covered by the instructor-led Week 1 plan

The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUEFoundation Assessment

2.0 h · 100 marks · Scripts + C++ transaction class

View assignment details →
WEEK 2

Verilog RTL I

Current learning scope

Focus: Combinational, arithmetic, sequential, counters, timers

Lab emphasis: Heavy RTL coding

Day 6Verilog RTL I – Fundamentals7h
Theory · 2h

Verilog module/ports/nets/variables
Operators and continuous assignment
Parameters; hierarchy and instantiation
Compilation and basic simulation flow

Guided Lab · 2h

1. AND/OR/XOR/XNOR
2. NAND/NOR
3. Multi-gate module
4. Half adder
5. Full adder
6. Full adder using half adders

Independent Lab · 2h

7. Half/full subtractor
8. 4-bit ripple adder
9. Parameterized N-bit adder
10. Comparator
11. Parity generator/checker

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Fix syntax, width, port and undeclared-signal bugs
Write one parameterized arithmetic block

Complete this work before closing Day 6.
WHAT YOU MUST COMPLETEExpected deliverable

Working RTL + basic TB for arithmetic blocks

Continue in Learn

The corresponding public course is not published yet.

Day 7Verilog RTL I – Combinational7h
Theory · 2h

always blocks and blocking assignment
if/else, case/casez/casex
Complete assignments and latch avoidance
Combinational coding guidelines

Guided Lab · 2h

1. 2:1 MUX with assign
2. 2:1 MUX with if
3. 2:1 MUX with case
4. 4:1/8:1 MUX
5. Decoder/DEMUX

Independent Lab · 2h

6. Encoder/priority encoder
7. Binary↔one-hot
8. Min/max selector
9. Leading-one/zero detector
10. Population counter
11. Parameterized MUX

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug missing default, incomplete assignment, bad slicing
Explain why each faulty block infers wrong hardware

Complete this work before closing Day 7.
WHAT YOU MUST COMPLETEExpected deliverable

Combinational RTL library

Continue in Learn

The corresponding public course is not published yet.

Day 8Verilog RTL I – Arithmetic/ALU7h
Theory · 2h

Signed vs unsigned arithmetic
Carry/borrow/overflow
Logical/arithmetic shifts
ALU structure and flag generation

Guided Lab · 2h

1. 4/8-bit adder
2. Carry-in adder
3. Add/sub block
4. Increment/decrement
5. Signed adder/comparator

Independent Lab · 2h

6. Absolute value
7. Logical/arithmetic shifters
8. Rotator
9. Barrel shifter
10. 8-operation ALU
11. Flags: C/Z/N/V
12. Parameterized ALU

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug overflow and signedness corner cases
Independent 16-bit ALU implementation

Complete this work before closing Day 8.
WHAT YOU MUST COMPLETEExpected deliverable

16-bit parameterized ALU + tests

Continue in Learn

The corresponding public course is not published yet.

Day 9Verilog RTL I – Sequential7h
Theory · 2h

Clocked always blocks
Non-blocking assignment
Sync/async reset
Enable/load/clear patterns
Shift registers

Guided Lab · 2h

1. DFF
2. Sync-reset DFF
3. Async-reset DFF
4. Enable DFF
5. 4/8-bit registers
6. Register with load/clear

Independent Lab · 2h

7. SISO/SIPO/PISO/PIPO
8. Bidirectional shift register
9. Universal shift register
10. Toggle FF
11. Edge detector
12. Pulse generator/stretcher

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug blocking/NBA misuse, reset polarity, clock edge
Waveform explanation exercise

Complete this work before closing Day 9.
WHAT YOU MUST COMPLETEExpected deliverable

Sequential RTL collection + waveforms

Continue in Learn

The corresponding public course is not published yet.

Day 10Verilog RTL I – Counters/Timers7h
Theory · 2h

Counter architectures
Modulo and terminal count
Timer/reload/timeout
Interrupt generation
Watchdog concept

Guided Lab · 2h

1. Up/down/up-down counters
2. Enable/load counter
3. MOD-10/MOD-N
4. Ring/Johnson/Gray counters
5. Free-running/event counters

Independent Lab · 2h

6. Clock divider
7. Programmable counter
8. One-shot timer
9. Periodic timer
10. Timeout generator
11. Timer IRQ
12. Watchdog timer

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-2 coding assessment
Mini-project: programmable timer with IRQ

Complete this work before closing Day 10.
WHAT YOU MUST COMPLETEExpected deliverable

Programmable timer RTL + TB

Continue in Learn

The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUEVerilog RTL I

2.5 h · 100 marks · RTL + TB + waveform

View assignment details →
WEEK 3

Verilog RTL II

Current learning scope

Focus: Parameterization, FSM, memories, FIFO, arbiter, interrupts

Lab emphasis: Reusable ASIC-style RTL

Day 11Verilog RTL II – Reuse7h
Theory · 2h

parameter/localparam
Functions and tasks
generate-for / generate-if
Hierarchical reusable RTL
Compile-time configuration

Guided Lab · 2h

1. Parameterized adder/MUX/comparator
2. Parameterized register/counter
3. Arithmetic/parity functions
4. Stimulus task
5. Generate register bank

Independent Lab · 2h

6. Generate adder array
7. Conditional generate
8. Multi-channel configurable design
9. WIDTH 8/16/32 reuse challenge
10. Parameter override at instantiation

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Fix bad parameter widths and generate conditions
Create reusable RTL package folder

Complete this work before closing Day 11.
WHAT YOU MUST COMPLETEExpected deliverable

Reusable parameterized RTL set

Continue in Learn

The corresponding public course is not published yet.

Day 12Verilog RTL II – FSM Intensive7h
Theory · 2h

FSM partitioning
Moore/Mealy
State encoding
Illegal-state recovery
Control-path verification

Guided Lab · 2h

1. 2-state/3-state FSM
2. Moore detector
3. Mealy detector
4. Overlap/non-overlap
5. Traffic controller
6. Pedestrian control

Independent Lab · 2h

7. Vending machine
8. Door controller
9. Elevator controller
10. Washing controller
11. Command processor
12. Handshake/timeout/retry
13. One-hot vs binary FSM

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug dead state, missing transition, lockup and reset-state bugs
Compare Moore vs Mealy waveforms

Complete this work before closing Day 12.
WHAT YOU MUST COMPLETEExpected deliverable

FSM portfolio + debug report

Continue in Learn

The corresponding public course is not published yet.

Day 13Verilog RTL II – Memories/Register Blocks7h
Theory · 2h

Register arrays; RAM/ROM models
Sync/async reads
Address decode and write enable
Config/status registers
W1C and sticky status concepts

Guided Lab · 2h

1. Register array
2. 8×8 and 16×32 register files
3. ROM
4. Single-port RAM
5. Sync read RAM

Independent Lab · 2h

6. Address/write-enable decode
7. Config/status/RO/WO/RW regs
8. W1C register
9. Sticky status
10. HW-set/SW-clear
11. Register bank integration

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug address aliasing and W1C behavior
Mini-project: config/status register block

Complete this work before closing Day 13.
WHAT YOU MUST COMPLETEExpected deliverable

Register block with read/write tests

Continue in Learn

The corresponding public course is not published yet.

Day 14Verilog RTL II – FIFO7h
Theory · 2h

FIFO architecture
Read/write pointers
Full/empty/occupancy
Overflow/underflow
Parameterized depth/width

Guided Lab · 2h

1. FIFO storage
2. Write pointer
3. Read pointer
4. Empty/full logic
5. Write/read operations
6. Simultaneous R/W

Independent Lab · 2h

7. Occupancy count
8. Overflow/underflow
9. Almost-full/empty
10. Param width/depth
11. Complete synchronous FIFO
12. FIFO error/status flags

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug pointer and full/empty off-by-one bugs
Independent configurable FIFO

Complete this work before closing Day 14.
WHAT YOU MUST COMPLETEExpected deliverable

Synchronous FIFO + status/error logic

Continue in Learn

The corresponding public course is not published yet.

Day 15Verilog RTL II – Arbiter/Interrupt7h
Theory · 2h

Fixed-priority arbitration
Round-robin concept
IRQ edge/level behavior
Mask/status/clear/priority
Aggregation

Guided Lab · 2h

1. 2/4-request arbiter
2. Fixed priority
3. Grant-hold logic
4. Round-robin exercise
5. Edge/level IRQ capture

Independent Lab · 2h

6. Sticky IRQ
7. IRQ status/enable/mask/clear
8. Multi-source IRQ
9. Priority IRQ
10. IRQ aggregation
11. 4-source interrupt controller

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-3 assessment: FIFO + FSM + IRQ debugging
Document register map for IRQ controller

Complete this work before closing Day 15.
WHAT YOU MUST COMPLETEExpected deliverable

4-source interrupt controller + assessment

Continue in Learn

The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUEVerilog RTL II

3.0 h · 100 marks · Advanced RTL block + debug evidence

View assignment details →
WEEK 4

Verilog Verification

Current learning scope

Focus: Testbenches, self-checking, regression, debugging

Lab emphasis: Verification + waveform debug

Day 16Verilog Verification – TB Fundamentals7h
Theory · 2h

Testbench architecture
DUT instantiation
Clock/reset generation
Tasks/functions
System tasks and waveform dumping

Guided Lab · 2h

1. AND-gate TB
2. DUT instantiation
3. Parameterized clock
4. Reset task
5. Directed stimulus
6. Loop stimulus

Independent Lab · 2h

7. Random stimulus
8. Driver task
9. Checker function
10. $display/$monitor/$strobe
11. $dumpfile/$dumpvars
12. PASS/FAIL counters

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Fix race-prone stimulus timing
Create reusable TB skeleton

Complete this work before closing Day 16.
WHAT YOU MUST COMPLETEExpected deliverable

Reusable Verilog TB template

Continue in Learn

The corresponding public course is not published yet.

Day 17Verilog Verification – Self-Checking7h
Theory · 2h

Expected-value generation
Reference model concept
Automatic checking
Boundary/corner testing
Result summaries

Guided Lab · 2h

1. Self-check adder/MUX/comparator
2. ALU reference model
3. Counter/shift register checkers
4. Timer checker
5. FSM checker

Independent Lab · 2h

6. Register-block checking
7. FIFO checker
8. Arbiter checker
9. IRQ controller checker
10. Auto summary TOTAL/PASS/FAIL/ERROR

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Inject one DUT bug and prove checker catches it
Write test plan for timer or FIFO

Complete this work before closing Day 17.
WHAT YOU MUST COMPLETEExpected deliverable

Self-checking TB + test plan

Continue in Learn

The corresponding public course is not published yet.

Day 18Verilog Verification – Advanced TB7h
Theory · 2h

Reusable tasks/functions
File I/O concepts
Memory initialization
Random seeds/repeat loops
Basic regression scripting

Guided Lab · 2h

1. Task library
2. Stimulus vector loop
3. Read test vectors from file
4. Write results to file
5. Memory preload

Independent Lab · 2h

6. Multi-test selection
7. Seeded random runs
8. Batch 10 simulations
9. Log naming
10. Regression summary extraction
11. Waveform-on-fail flow

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug non-reproducible random failure using seed
Build 5-test mini regression

Complete this work before closing Day 18.
WHAT YOU MUST COMPLETEExpected deliverable

Automated mini regression

Continue in Learn

The corresponding public course is not published yet.

Day 19Verilog Verification – Debug Bootcamp7h
Theory · 2h

Compile/elaboration/simulation failures
X/Z propagation
Width/signedness issues
Race conditions
RTL vs TB root cause

Guided Lab · 2h

1. Syntax bug
2. Port mismatch
3. Width mismatch
4. Signed arithmetic bug
5. Blocking/NBA bug
6. Missing combinational assignment

Independent Lab · 2h

7. Reset polarity bug
8. Counter off-by-one
9. FSM lockup
10. Multiple driver
11. FIFO pointer bug
12. TB timing race
13. X-propagation analysis

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

For each failure: reproduce → log → waveform → root cause → patch → rerun
Prepare bug report with evidence

Complete this work before closing Day 19.
WHAT YOU MUST COMPLETEExpected deliverable

RTL/DV debug report

Continue in Learn

The corresponding public course is not published yet.

Day 20Verilog Verification – Integration7h
Theory · 2h

Verification planning
Requirements-to-tests mapping
Regression discipline
Review and coding quality

Guided Lab · 2h

1. Integrate timer/register/IRQ blocks
2. Build top-level TB
3. Directed smoke tests
4. Negative tests
5. Boundary tests

Independent Lab · 2h

6. Random test loop
7. Regression script
8. Waveform debug
9. Clean PASS/FAIL report
10. Code review and lint-style checklist

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-4 practical assessment
Mini-project demonstration

Complete this work before closing Day 20.
WHAT YOU MUST COMPLETEExpected deliverable

Verified Verilog mini-system + regression report

Continue in Learn

The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUEVerilog Verification

3.0 h · 100 marks · Automated testbench + report

View assignment details →
WEEK 5

SystemVerilog Language

Coming Soon

Focus: Data types, arrays, OOP, processes, IPC

Lab emphasis: Language mastery

Day 21SystemVerilog Language – Data Types7h
Theory · 2h

Verilog vs SystemVerilog
2-state/4-state types
logic/bit/byte/int/longint
Packed/unpacked arrays
typedef

Guided Lab · 2h

1. logic vs bit
2. 2-state vs 4-state behavior
3. Packed arrays
4. Unpacked arrays
5. Multi-dimensional arrays

Independent Lab · 2h

6. typedef aliases
7. Signed data types
8. Casting exercises
9. String basics
10. Packet field representation

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug type-width and cast issues
Convert a Verilog TB data model to SystemVerilog

Complete this work before closing Day 21.
WHAT YOU MUST COMPLETEExpected deliverable

SV datatype exercise set

Continue in Learn

The corresponding public course is not published yet.

Day 22SystemVerilog Language – Collections7h
Theory · 2h

Dynamic arrays
Queues
Associative arrays
Array methods
enum/struct/union
foreach

Guided Lab · 2h

1. Dynamic allocate/resize
2. Queue push/pop/insert/delete
3. Queue search/sort
4. Associative address map
5. foreach loops

Independent Lab · 2h

6. enum state/opcode
7. struct packet
8. union storage demo
9. Array reduction methods
10. Transaction queue
11. Scoreboard-style associative store

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug out-of-range and empty-queue cases
Build packet database utility

Complete this work before closing Day 22.
WHAT YOU MUST COMPLETEExpected deliverable

SV collections utility

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The corresponding public course is not published yet.

Day 23SystemVerilog OOP I7h
Theory · 2h

Class/object/handle
Constructor and this
Methods
Object assignment
Copy/compare/print concepts

Guided Lab · 2h

1. Basic packet class
2. Object creation
3. Constructor
4. this keyword
5. Display method
6. Copy method

Independent Lab · 2h

7. Compare method
8. Object handle assignment
9. Null-handle handling
10. Array of objects
11. Queue of objects
12. Transaction utility class

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug null handle and shallow copy issue
Build reusable transaction class

Complete this work before closing Day 23.
WHAT YOU MUST COMPLETEExpected deliverable

OOP transaction library

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The corresponding public course is not published yet.

Day 24SystemVerilog OOP II7h
Theory · 2h

Inheritance
Polymorphism
Virtual methods/classes
local/protected/static
Parameterized classes
Composition

Guided Lab · 2h

1. Base/read/write transactions
2. Override display/compare
3. Base handle + derived object
4. Virtual method demo
5. Static object counter

Independent Lab · 2h

6. Protected/local members
7. Parameterized transaction
8. Class composition
9. Abstract-style base class exercise
10. Factory-like manual creation exercise
11. Deep-copy hierarchy

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug slicing/override mistakes
Create extensible packet hierarchy

Complete this work before closing Day 24.
WHAT YOU MUST COMPLETEExpected deliverable

Advanced OOP class hierarchy

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The corresponding public course is not published yet.

Day 25SystemVerilog Processes & IPC7h
Theory · 2h

fork/join variants
Process synchronization
events
mailboxes
bounded mailbox
semaphore
Producer/consumer

Guided Lab · 2h

1. fork...join
2. join_any
3. join_none
4. wait fork
5. disable fork
6. Event trigger/wait

Independent Lab · 2h

7. Mailbox put/get/try_get
8. Bounded mailbox
9. Semaphore lock
10. Producer-consumer
11. Parallel stimulus
12. Timeout/watchdog process

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug mailbox deadlock and runaway process
Week-5 assessment: OOP + IPC

Complete this work before closing Day 25.
WHAT YOU MUST COMPLETEExpected deliverable

Concurrent SV stimulus framework

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The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUESV Language/OOP

2.5 h · 100 marks · Transaction/OOP exercise

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WEEK 6

SystemVerilog Verification

Coming Soon

Focus: Interfaces, TB architecture, constraints

Lab emphasis: Transaction-based verification

Day 26SystemVerilog Verification – Interfaces7h
Theory · 2h

interface
modport
clocking blocks
Virtual interface concept
Signal direction and sampling discipline

Guided Lab · 2h

1. Basic interface
2. DUT connection
3. Driver modport
4. Monitor modport
5. Clocking block

Independent Lab · 2h

6. Input/output skew experiment
7. Parameterized interface
8. Interface tasks
9. Multiple interface instances
10. Virtual-interface handle exercise
11. Race-free drive/sample

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug wrong modport and clocking direction
Refactor raw-pin TB to interface-based TB

Complete this work before closing Day 26.
WHAT YOU MUST COMPLETEExpected deliverable

Interface-based verification harness

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The corresponding public course is not published yet.

Day 27SystemVerilog Verification – TB Architecture7h
Theory · 2h

Transaction-based verification
Generator/driver/monitor
Scoreboard/reference model
Mailbox communication
Environment layering

Guided Lab · 2h

1. Transaction class
2. Generator
3. Generator→driver mailbox
4. Driver
5. Monitor

Independent Lab · 2h

6. Monitor→scoreboard path
7. Reference model
8. Actual/expected compare
9. Environment class
10. End-of-test statistics
11. Error injection
12. Complete ALU/FIFO environment

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug a scoreboard mismatch
Draw and document TB architecture

Complete this work before closing Day 27.
WHAT YOU MUST COMPLETEExpected deliverable

Complete non-UVM SV environment

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The corresponding public course is not published yet.

Day 28SystemVerilog Randomization I7h
Theory · 2h

rand/randc
Basic constraints
inside
Ranges and exclusions
Inline constraints
pre/post_randomize

Guided Lab · 2h

1. Random address/data
2. rand vs randc
3. Range constraint
4. inside set
5. Exclusion constraint
6. Aligned address

Independent Lab · 2h

7. Legal opcode
8. Boundary values
9. Inline constraint
10. pre_randomize
11. post_randomize
12. 1,000 transactions

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug impossible constraint
Create constrained transaction generator

Complete this work before closing Day 28.
WHAT YOU MUST COMPLETEExpected deliverable

Constrained random generator

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The corresponding public course is not published yet.

Day 29SystemVerilog Randomization II7h
Theory · 2h

Conditional/implication constraints
dist
solve before
soft constraints
Array constraints
Constraint inheritance/control

Guided Lab · 2h

1. Conditional constraint
2. Implication
3. Weighted dist
4. solve-before
5. soft constraint

Independent Lab · 2h

6. Dynamic-array size constraint
7. Array element constraints
8. Unique values
9. Constraint inheritance
10. constraint_mode
11. random_mode
12. Error-traffic generation

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Analyze 5 randomization failures
Build legal + illegal transaction profiles

Complete this work before closing Day 29.
WHAT YOU MUST COMPLETEExpected deliverable

Advanced constraint library

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The corresponding public course is not published yet.

Day 30SystemVerilog Verification – Mini Project7h
Theory · 2h

Verification plan creation
Stimulus/checker separation
Random + directed blend
Regression and debug workflow

Guided Lab · 2h

1. Select FIFO or timer DUT
2. Build interface
3. Transaction/generator/driver
4. Monitor/scoreboard

Independent Lab · 2h

5. Directed tests
6. Random tests
7. Error tests
8. Boundary tests
9. 10-seed regression
10. Failure triage
11. Final report

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-6 practical assessment
Peer review of architecture and code

Complete this work before closing Day 30.
WHAT YOU MUST COMPLETEExpected deliverable

Complete SV verification mini-project

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The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUESV Verification

3.0 h · 100 marks · Complete SV environment

View assignment details →
WEEK 7

SVA & Coverage

Coming Soon

Focus: Assertions, functional coverage, closure

Lab emphasis: Coverage-driven verification

Day 31SystemVerilog Assertions – Fundamentals7h
Theory · 2h

Immediate vs concurrent assertions
Sequence/property
|-> and |=>
## delays
disable iff
Pass/fail reporting

Guided Lab · 2h

1. Immediate check
2. Reset property
3. Known-value check
4. One-hot
5. Onehot0
6. Mutual exclusion

Independent Lab · 2h

7. Req→ack same/next cycle
8. Response within N cycles
9. Stable data
10. Pulse-width check
11. Reset disables property
12. Simple sequence composition

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug vacuous/incorrect property
Add 8 assertions to timer/FIFO

Complete this work before closing Day 31.
WHAT YOU MUST COMPLETEExpected deliverable

Assertion set with pass/fail evidence

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The corresponding public course is not published yet.

Day 32SystemVerilog Assertions – Advanced7h
Theory · 2h

Repetition operators
throughout/within concepts
FSM and protocol checks
FIFO safety properties
Latency/error properties

Guided Lab · 2h

1. Consecutive repetition
2. Non-consecutive repetition
3. FSM legal state
4. No-write-on-full
5. No-read-on-empty

Independent Lab · 2h

6. FIFO count bounds
7. Timer timeout property
8. IRQ latency
9. IRQ clear behavior
10. Handshake ordering
11. Data stability under wait
12. Error recovery

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug 6 intentionally wrong properties
Create assertion plan mapped to requirements

Complete this work before closing Day 32.
WHAT YOU MUST COMPLETEExpected deliverable

Advanced SVA property suite

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The corresponding public course is not published yet.

Day 33Functional Coverage – Fundamentals7h
Theory · 2h

covergroup/coverpoint
Automatic/explicit bins
Range/wildcard/transition bins
Sampling
Coverage options

Guided Lab · 2h

1. Basic covergroup
2. Data bins
3. Address bins
4. Opcode bins
5. Range bins
6. Boundary bins

Independent Lab · 2h

7. Wildcard bins
8. Transition bins
9. Illegal bins
10. Ignore bins
11. Manual sample
12. Event-based sampling
13. Per-instance exercise

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Find why expected bin is not hit
Create coverage model for ALU/FIFO

Complete this work before closing Day 33.
WHAT YOU MUST COMPLETEExpected deliverable

Functional coverage model

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The corresponding public course is not published yet.

Day 34Functional Coverage – Cross & Closure7h
Theory · 2h

Cross coverage
Conditional coverage
Coverage holes
Constraint tuning
Coverage closure workflow
Coverage reporting

Guided Lab · 2h

1. op×data cross
2. addr×op cross
3. state×event cross
4. FIFO occupancy coverage
5. IRQ coverage

Independent Lab · 2h

6. Conditional iff coverage
7. Run random baseline
8. Identify holes
9. Modify constraints
10. Directed closure test
11. Re-run coverage
12. Closure report

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Explain each uncovered bin and closure action
Target ≥ planned coverage threshold

Complete this work before closing Day 34.
WHAT YOU MUST COMPLETEExpected deliverable

Coverage closure report

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The corresponding public course is not published yet.

Day 35Integrated SystemVerilog Verification7h
Theory · 2h

Integrating interfaces/OOP/random/SVA/coverage
Regression architecture
Debug discipline
Requirements traceability

Guided Lab · 2h

1. Integrate transaction TB
2. Add constrained random
3. Add assertions
4. Add functional coverage
5. Add scoreboard

Independent Lab · 2h

6. 20-seed regression
7. Inject RTL bug
8. Detect via checker/SVA
9. Analyze coverage
10. Close hole
11. Generate final SV report

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Week-7 assessment
Prepare architecture presentation

Complete this work before closing Day 35.
WHAT YOU MUST COMPLETEExpected deliverable

Full SV verification environment + regression

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The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUESVA/Coverage

3.0 h · 100 marks · SVA + coverage closure report

View assignment details →
WEEK 8

UVM & Final Integration

Coming Soon

Focus: UVM components, advanced UVM, regression, final project

Lab emphasis: Reusable methodology

Day 36UVM – Fundamentals7h
Theory · 2h

UVM architecture and hierarchy
uvm_object vs uvm_component
uvm_sequence_item
Factory registration
Phases and reporting

Guided Lab · 2h

1. UVM hello
2. Sequence item
3. Factory registration
4. print/copy/compare
5. Basic component

Independent Lab · 2h

6. build/connect/run/report phases
7. Hierarchy print
8. uvm_info/warning/error/fatal
9. Transaction field automation
10. Simple test/env hierarchy

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug missing registration/phase issue
Create minimal compiling UVM testbench

Complete this work before closing Day 36.
WHAT YOU MUST COMPLETEExpected deliverable

UVM skeleton environment

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The corresponding public course is not published yet.

Day 37UVM – Sequence/Sequencer/Driver7h
Theory · 2h

Sequence/sequence item
Sequencer
Driver
start_item/finish_item
get_next_item/item_done
Sequence control

Guided Lab · 2h

1. Directed sequence
2. Random sequence
3. Reset sequence
4. Boundary sequence
5. Error sequence

Independent Lab · 2h

6. Stress sequence
7. Sequencer
8. Driver
9. seq_item_port connection
10. Drive DUT via virtual interface
11. 100/1000 item sequence
12. Sequence reuse

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug sequence not starting / item_done hang
Create sequence library

Complete this work before closing Day 37.
WHAT YOU MUST COMPLETEExpected deliverable

Working sequence→driver path

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The corresponding public course is not published yet.

Day 38UVM – Monitor/Agent/Scoreboard7h
Theory · 2h

Monitor and analysis ports
Active/passive agent
Scoreboard/reference model
Environment and test
Analysis connectivity

Guided Lab · 2h

1. Monitor
2. Analysis port
3. Scoreboard
4. Expected model
5. Compare actual/expected

Independent Lab · 2h

6. Active agent
7. Passive agent
8. Agent config
9. Environment
10. Test class
11. Error injection
12. Statistics/report phase

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug disconnected analysis path
Build complete UVM agent + scoreboard

Complete this work before closing Day 38.
WHAT YOU MUST COMPLETEExpected deliverable

Complete UVM environment

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The corresponding public course is not published yet.

Day 39UVM – Advanced + Regression7h
Theory · 2h

uvm_config_db
Virtual interface
Config objects
Factory overrides
Objections
Subscribers/coverage
Regression/debugging

Guided Lab · 2h

1. config_db set/get
2. Virtual interface
3. Config object
4. Object override
5. Component override

Independent Lab · 2h

6. Objections
7. Coverage subscriber
8. Assertions integration
9. Smoke/reset/boundary/random/error/stress tests
10. Regression script
11. Log triage
12. UVM debug cases

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Debug null VIF, bad config_db, wrong override, scoreboard mismatch
Run multi-test regression

Complete this work before closing Day 39.
WHAT YOU MUST COMPLETEExpected deliverable

Advanced UVM regression + report

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The corresponding public course is not published yet.

Day 40Final Integrated Project & Evaluation7h
Theory · 2h

End-to-end requirements→RTL→verification
Design review and verification review
Regression sign-off mindset
Technical presentation/viva

Guided Lab · 2h

1. Integrate configurable timer + register block + IRQ
2. UVM env hookup
3. Directed smoke/reset/register tests
4. Assertions

Independent Lab · 2h

5. Random/boundary/error/stress tests
6. Functional coverage
7. Regression
8. Bug injection and debug
9. Coverage closure
10. Final results package

TODAY’S ASSIGNMENT / DEBUG WORK1 hour

Final coding assessment + viva
Present architecture, tests, bugs, coverage and regression results

Complete this work before closing Day 40.
WHAT YOU MUST COMPLETEExpected deliverable

Final project package + presentation + score

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The corresponding public course is not published yet.

WEEKLY ASSIGNMENT DUEUVM + Final

Full day · 200 marks · Code + regression + presentation

View assignment details →
Assessment plan

Assignments are placed at the end of the skill stage they assess.

See weekly assessment deliverables, pass expectations, final project and evaluation weightage.

View assignments & evaluation →