Verilog RTL II
FSM/FIFO/register/interrupt
Assessment timing: End of Week 3, after Day 15.
Workbook requirement
Primary deliverable
Advanced RTL block + debug evidence
Workbook expectation
Pass expectation
Correct function + clean coding
01Complete Week 3 learning
→02Finish guided & independent labs
→03Debug and verify
→04Prepare deliverable
→05Assessment / review
This page currently defines the workbook assessment requirement. Detailed question-level assessment content has not yet been authored for this week.